The invention relates to an integrated matrix memory including a circuit arrangement for testing the addressing of the matrix. The matrix includes elements which are arranged at intersections of row conductors and column conductors, wherein the addressing takes place by way of a multibit address via a decoder. The decoder has at least one row decoder and one column decoder each of which is conceived to receive and decode a different pan of the address bits and to drive each time a different row conductor to or select at least one column conductor, via selection switches, for connection to at least one output terminal.
The storage elements arranged at the intersections of row conductors and column conductors in integrated semiconductor matrix memories are constructed in various ways. After manufacturing storage elements which can be read as well as written at a high speed, the memory is generally tested such that various bit patterns are written into the storage cells and read again, the bit patterns read being tested for correctness. The testing of the addressing of such memories is, therefore, indirect. Memories of this kind, however, generally lose their contents when the supply voltage is interrupted. An example of memories which save their contents in the absence of a supply voltage are the so-called programmable memories whose contents can be written once, after which they cannot easily be modified if at all. For such memories it would be effective to test, prior to the time-consuming writing of the contents, whether the separate addressing of the individual storage elements functions correctly, so that faulty memories can be rejected prior to writing. Another example of such memories, referred to as EEPROM's which have contents which can be electrically modified but are saved after interruption of the supply voltage. The writing and erasure of such memories, however, requires a substantial mount of time so that the writing of different bit patterns with subsequent reading and testing is very time consuming. Prior testing of the correct operation of the addressing of the individual storage elements would also be very efficient for such memories.
From EP-480 752 A1 there is known a circuit arrangement for testing semiconductor matrix memories with respect to of short circuits between neighboring leads. To this end, a signal is applied to every second row conductor or every second column conductor and it is tested whether this signal occurs, or a current flows, in the intermediate row conductors or column conductors. Such a test, however, is imperfect because it is not suitable to determine interruptions in the leads and because the decoder is not tested.